The NTE is a monolithic 4-line-toline decoder in a Lead DIP type The NTE is fully compatible for use with most other TTL and DTL circuits. MOS technology. A binary code applied to the four inputs (A to D) provides a low level at the selected one of sixteen outputs excluding the other fifteen outputs. SNN .. of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration.
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Sign up using Facebook. Rather than providing only a single enable, both pins are used.
4 to 16 decoder logic diagram – Electrical Engineering Stack Exchange
For example, if the target application requires 16 7-segment LED displays, but your microcontroller only has 4 lines to select which display is active, this chip 74LS would provide a very effective method of essentially multiplying you selecting lines by a 4 times.
The LED can be chosen at random by the status of the 4 line selector inputs. Will someone please explain the purpose of inverting the outputs 0 through 15 as well as the use the NAND gates here?
National Semiconductor – datasheet pdf
However, due to the internal structure of theonly one output can be enabled at a time. Home Questions Tags Users Unanswered.
These demultiplexers are ideally suited for implementing high-performance memory decoders. First, the inversion of the outputs simply means that the output is active low. Post as a guest Name.
As for the NAND gates, there is a function being implemented in which datasgeet gates are there to realize it. According to the internal logic diagram on the datasheet, the G inputs are connected to a two-input AND gate with inverting inputs, whose output feeds one input of all the NAND gates that produce the outputs. This allows more flexibility in the logic functions available. Email Required, but never shown. Each of the 16 outputs can be connected through a resistor and then through an Dztasheet to serve as a simple 16 LED controller.
Many TTL parts and older memory chips have active low enable inputs, so the active low outputs of this part can be connected directly to those inputs.
That is, for an input ofthe 0 output is selected, and it is driven low. The active-low enable inputs allow cascading of demultiplexers over many bits.
WhatRoughBeast 49k 2 28 That is, if the outputs were active high, OR gates would perform the synthesis desired. So is it possible that both enables are hooked to a 2-input OR gate; this is just making use of the extra pins to make 24?
Since the ouputs are active low, NAND gates do the job. All the other ouputs stay high.
74154 Datasheet PDF
I am a new user so I didn’t know I had that power. If you wanted to generate a 1 of demultiplexer, you could use 16 s looking at the 4 least significant bits, while a single would look at the 4 most significant bits, with one ouput going to each of the other 16 s.
Understand, this is a typical example of application, not it’s sole purpose.